1. Field of the Invention
The present invention relates to a reference voltage generator for a device, e.g., a frequency divider, and a method of supplying a reference voltage. More particularly, the present invention relates to a reference voltage generator that generates a reference voltage to be applied to the device and a method of supplying a reference to the device.
2. Description of the Related Art
Generally, a frequency synthesizer used in a radio frequency (RF) system is used to lock a local oscillation frequency output from a voltage controlled oscillator (VCO) to a selected channel frequency. Typically, a frequency synthesizer is constructed with a phase locked loop (PLL).
FIG. 1 is a block diagram of a PLL. The PLL of FIG. 1 includes a phase detector (PD) 10, a charge pump 11, a loop filter 12, a VCO 13, a pre-scaler 14, and a frequency divider 15.
The PD 10 detects the phases of a reference frequency and a frequency output from the frequency divider 15 and outputs a pulse corresponding to a difference between the phases. The charge pump 11 outputs charges to a capacitor (not shown) in the loop filter 12 corresponding to a width of a positive pulse output from the PD 10 or receives charges corresponding to a width of a negative pulse from the capacitor. The loop filter 12 discharges/accumulates electric charges to/from the charge pump 11 to control a voltage. The loop filter 12 generally includes a low-pass filter for performing low-pass filtering to output a low frequency component of voltage. The VCO 13 outputs a specific frequency according to a voltage received from the loop filter 12. The pre-scaler 14 divides an output frequency of the VCO 13 by one of two fixed ratios and outputs a frequency lower than the frequency output by the VCO 13. The division ratio of the pre-scaler 14 is dependent on a mode control signal. The divider 15 divides a frequency output from the pre-scaler 14 so that the divided frequency output from the divider 15 is substantially the same as the reference frequency, and outputs the divided result to the PD 10.
In more detail, the pre-scaler 14 may include a 4/5 synchronous divider (shown in FIG. 2) and an 8 asynchronous divider (not shown). As shown in FIG. 2, the 4/5 synchronous divider is constructed by cascading a plurality of D flip-flops (DFFs). As seen in FIG. 2, the 4/5 synchronous divider includes a first DFF 21, a first NOR gate 20 that supplies an input signal to the first DFF 21, a second DFF 22, a third DFF 24, and a second NOR gate 23 that supplies an input signal to the third DFF 24. The first through third DFFs 21, 22, 24, each receive a clock signal CK and an inverted clock signal CKB. A reference voltage (DBIAS) is provided to the first DFF 21 and the third DFF 24.
An output signal of a terminal Q of the second DFF 22 and an output signal of a terminal QB of the third DFF 24 are supplied as input signals to the first NOR gate 20. Also, an output signal of a terminal QB of the second DFF 22 and a mode control signal MC are supplied as input signals to the second NOR gate 23. The first DFF 21 outputs a divided-by-two signal for each clock cycle and the second DFF 22 outputs a divided-by-four signal for each clock cycle. The third DFF 24 maintains the output signal of the second DFF 22 while the mode control signal MC is high, and performs division-by-five when the mode control signal MC is low.
When a DFF serves to directly receive and divide a signal in the GHz band, such a DFF may not be implemented with complementary metal-oxide semiconductor (CMOS) logic gates. Instead, a DFF for use in this frequency band may be implemented using current mode logic (CML).
CML is a logic gate implemented using a differential amplifier pair. Since a reference voltage (DBIAS) of a CML is set so that the amplitude of a signal can be kept constant, a CML can operate at a very high speed. Such a DFF allows an edge trigger operation by cascading two D-latches each implemented with CML in a cascade form so that the two D-latches act as a master and a slave, respectively.
However, when changes occur in a manufacturing process due to manufacturing tolerances, the characteristics of CML and resistors constructing CML are altered. For example, the resistances of the resistors may be changed by up to 20%. A DFF output voltage may also get changed, since the reference voltage DBIAS supplied to a DFF cannot follow changes in the amplitude of an input signal because the reference voltage DBIAS is a fixed value.